Chapter 5: Processor Fundamentals

Dec 15, 2019

Overview of the chapter

This chapter is the further extension of “Computer Architecture” in IGCSE.

This is a small chapter. Mr. Luke finished all of it in just one double-period!

SectionSub-sectionPage No.
5.1 Von Neumann Architecture5.1.1 Structure Overview2
5.2.2 CPU Architecture
-> Control Unit
-> ALU
-> Registors
2
5.2.3 Busses
-> Control Bus
-> Data Bus
-> Address bus
-> USB
3
5.2 Fetch-execute cycle4
5.3 Interrupt Handling5

Next page: 5.1 Von Neumann Architecture

5.1 Von Neumann Architecture

The Architecture requires the following characteristics:

  • Processor
    • Has a center processing unit
    • Has direct access to memory
    • Executes instructions in sequence
  • Memory
    • Stores stored programs and data required. They are stored in same memory and treated the same.

5.1.2 Processor Structure

The processor consists of two sections:

CPU (purple) and

Registers (red).

Structure of a CPU, from Computer Science Textbook

Central Processing Unit

Consists of two components: Control Unit and ALU.

Control UnitALU
Functions1. Control flow of data through processor — and whole computer.1. Handles any Arithmetic / Logic processing operation.
2. Synchronize actions of the processor.

Consists of two clocks to synchronize processes.
– The internal clock controls cycle of activities within processor
– The system clock controls activities outside the processor

The clocks have defined frequency called clock speed. It defines the minimum period of time that separates successive activities in the system.
(For example, for a 1MHz CPU, there can be only max. 1 million operations per second.)
3. Decodes instructions for execution.

Registers

Main article: 
5.2 Fetch-decode-execute cycle (-> Page 4)

Registers are storage components. Their proximity to ALU provides fast access speed.

There are two types of register: General-purpose and Special-Purpose.

The accumulator is the only type of general-purpose register.

Next page: 5.1.3 Busses

5.1.3 Busses

Parallel, synchronized transmission device. It allows data transmission in CPU, with I/O and memory.

The number of bytes handled as a unit is called a word. Ideally the bus width should be same as word length — during the transmission each wire in the bus carries a bit for parallel transmission.

Address BusData BusControl Bus
DirectionUnidirectional
CPU --> Memory


Bidirectional
I/O <-> CPU <-> Memory


(For some systems data from I/O
can be written into memory directly)
Bidirectional
I/O <-> CPU <-> Memory


CarriesAn addressData:
* Instruction
* Address or
* A value.
* Control signals
* Timing signals for sync.

USB: Universal Serial Bus

Serial, not synced, bi-directional data transmission.

  • Shows the plug-and-play concept
  • A hierarchy of connection is supported, max. 127 devices.
  • Device can be attached / detached while device is on.
    • Drivers can be automatically installed for use
  • Current standard USB 3.0

Next page: 5.2 Fetch-decode-execute cycle

5.2 Fetch-decode-execute cycle

This diagram describes how the cycle works.

The fetch-decode-execute cycle does normal operation.

After each cycle it checks for any interrupts. If there is any, the system will handle it.

This is a summary of the registers used in the cycle. We will look at them one by one in detail.

Summary of Some special-purpose registers.

5.2.1 Fetch Cycle

RegistersAbbreviationFunction
1. Program CounterPCStores the address of next instruction
2. Index RegisterIXStores the amount PC will increment after the cycle — for the next data address.
3. Memory Address RegisterMARStores the address of a memory that is going to be read / write from
4. Memory Data RegisterMDRStores the data of a memory that
* Is going to be written into memory
* Has just been read from the memory

Trace Table

Here is a trace table of fetching the information from address 101. The information stored in address 101 is a command “LDA 111”.

StepPseudocode
for understanding only
PC dataIX dataMDR dataMAR dataCIR data
0: PC stores address of next instruction10114
1: Address is transferred to MDRMDR <- [PC]10114101
2: The control unit sends command to RAM for reading data
through control bus.

The address stored in MDR is sent to RAM through data bus.
RAM <-(bus)- control unit
RAM <-(bus)- [MDR]
10114101
Steps 3.1 and 3.2 happens simultaneously;
3.1: The RAM sends data stored in that memory address to MAR.
MDR <-(bus)- [RAM]

Or usually, 3.1 is combined with step 2:
MDR <- [[MAR]]
Note the double brackets!
10114LDA 111101
3.2: The PC is incremented for next instructionPC <- [PC] + [IX]11514LDA 111101
4: [For commands only]
The command is sent from MDR to CIR for next stage: Decode.
CIR <- MDR11514LDA 111101LDA 111

5.2.2 Decode cycle

If the data fetched is a commend, then it is sent and stored in CIR.

The control unit then decodes it. The ALU will be activated for any arithmetic / logic calculations.

RegistersAbbreviationFunction
1. Current Instruction Register CIRStores current instruction for decoding and execution.

5.2.3 Execute cycle

Main article: Chapter 6, Assembly language programing

If the data requires calculation, then it is executed in the ALU unit.

RegistorsAbbreviationFunction
1. Accumulator
(The only General-purpose register)
ACCStores the value before and after ALU operation.

5.2.4 Other registers

RegistersAbbreviationFunction
1. Status RegisterSRContains a combination of bits to indicate results, e.g.
a) Overflow
b) Carry bit
c) Interrupt received

Next page: 5.3 Interrupts

5.3 Interrupts

A signal sent to the processor, seeking for its attention.

Different interrupts have different priorities. Interrupt is only detected at the end of fetch-execute cycle by checking status register.

After detection of interrupt the interrupt service routine (ISR) is initiated. Its start address is loaded into PC, and a fetch-decode-execute cycle for the ISR will be started.

After handling all interrupts the original program is reloaded into the registers, and the original program is resumed.

Examples of interrupts

  • Software
    • Fatal Error
    • User interrupt (Ctrl + Alt + Del)
    • Timer signal
  • Hardware fault
    • Request of I/O to begin
    • Paper jam

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